Modern integrated circuits (ICs) have a profound impact on society because of the high growth in consumer electronics (i.e. cell phones and laptops). The key device in ICs, which functions as switches in logic gates, is the silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). For the past four decades, continuous scaling of MOSFETs and interconnects has dramatically improved the performance of microprocessors and memory chips used in many consumer electronic products. However, it is increasingly difficult to scale Si MOSFETs because Hf-based gate oxide is approaching its limit due to power constraint and mobility degradation. Si CMOS has entered an era of “power-constrained scaling”. Without scaling gate oxide, high-mobility channel materials (III-V compound semiconductors) are needed for MOSFETs to enable increased performance and reduced power consumption.
In recent years, significant progress on III-V gate stacks has been made but huge challenges still remain. The interface trap density (Dit) between high-k oxides and InxGa1−xAs still remains too high (1011-1013 cm−2), especially near valence band. On one hand, this results in lower mobility (<2000 cm2/v-sec) for InxGa1−xAs inversion-mode n-MOSFETs. On the other hand, it is difficult to realize InxGa1−xAs p-MOSFETs. It is of critical importance to find a new approach for passivation of InGaAs to achieve low interface trap density (<1×1011 cm−2) so that both n-MOSFETs and p-MOSFETs can be realized using the same material system.
In the past GaAs has been passivated using Si interfacial layers grown by PECVD. Excellent high-frequency and quasi-static C-V curves were obtained on Si3N4/Si/p-GaAs with Dit, in the mid 1010 cm−2. It is the strained Si interlayer and the “clean” in-situ process that resulted in superior interfacial properties. The principle for superior Si3N4/Si/GaAs interface is that in the strained Si/GaAs interface the strained Si lattice is closely matched with GaAs. However, the in-situ process is a severe constraint for device processing.
This document relates to an ex-situ process technology for semiconductor heteroepitaxy using oxide deposition, oxygen scavenging, and crystallization